1. Field of the Invention
This invention relates to FIFO (First In/First Out) memories, and more particularly relates to an improved pull through FIFO memory system.
2. Description of Related Art
FIFO memories are widely used as intermediate buffers where there is a need to transfer binary data between systems or devices which operate at different frequencies and where the order of the data must remain unchanged. These devices are often constructed of multiple shift register stages coupled for cascade operations. Data is clocked into the first shift register stage at some shift in frequency, and after a certain latency time or fall through delay, the data is clocked out of the last stage at a different shift out frequency. The fall through delay is the time it takes for data to propagate through the FIFO, from input to output.
In the prior art, FIFO's are implemented using a RAM (random access memory) structure that includes a write pointer and a read pointer to store and keep track of the available and occupied locations. Therefore, additional logic is required to increment and decrement the pointers once data has been written to or read from the FIFO. For example, in order for a RAM based FIFO to keep track of the data in each stage of the FIFO, a RAM based FIFO with d stages would require log 2(d) input/outputs (I/O's). Moreover, in order to provide a system wherein data could be written and read simultaneously, a RAM based FIFO would require two-ported RAM's, which are physically larger than a single ported RAM and require {2 * log 2(d)} I/O's for the address, and {2 * w} I/O's for the data, where w is the size of each data word in bits. Accordingly, there is a need to provide a FIFO data storage structure that eliminates the need for RAM and write and read pointers.